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Harshith Reddy

Undergraduate · Bits Pilani

Hi! I am an 4th year undergraduate student at Bits Pilani, Pilani Campus. I have previously interned with Texas Instruments on the front-end of high-speed ADCs.

My broad research interests include Analog/RF/Mixed-Signal Integrated Circuit Design – in particular, I am interested in Wireless/Wireline/Optical Transceivers and Biomedical and RADAR imaging.


Publications

Conferences

  • A 40 GHz Low-Power Variable-Gain Low Noise Amplifier in 28-nm CMOS Process Dec, 2025
    Harshith Reddy and Pankaj Arora
    13th IEEE International Conference on IEMECON

    PDF     


  • A 16.28 ppm/°C Temperature Coefficient, 0.5V Low-Voltage CMOS Voltage Reference
    with Curvature Compensation
    Aug, 2025
    Harshith Reddy and Pankaj Arora
    29th International Symposium on VLSI Design and Test (VDAT)

    PDF     


SOP

    Coming Soon!

Service

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